1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device operating in synchronization with a clock signal consisting of a series of externally supplied pulses, and more particularly to a configuration of an internal voltage generating circuit for generating an internal voltage.
2. Description of the Background Art
FIG. 22 is a diagram schematically showing an entire configuration of a conventional synchronous semiconductor device. Shown in FIG. 22 is a configuration of a clock synchronous semiconductor memory device, as an example of a synchronous semiconductor device, which takes in an external signal and outputs data in synchronization with an external clock signal ext.CLK.
With reference to FIG. 22, a clock synchronous semiconductor memory device 100 includes a memory array 102 having a plurality of memory cells arranged in rows and columns; a clock input buffer 104 for buffering an externally supplied clock signal ext.CLK to generate an internal clock signal CLK; a command decoder 106 for taking in external control signals, i.e., a row address strobe signal /RAS, a column address strobe signal /CAS and a write enable signal /WE, in synchronization with internal clock signal CLK from clock input buffer 104, and generating an operation mode designating signal based on a combination of states of these control signals at a rising of internal clock signal CLK; and a control circuit 108 responsive to the operation mode designating signal from command decoder 106 for performing control necessary for execution of the designated operation mode in synchronization with internal clock signal CLK. Command decoder 106 determines the combination of the states of the control signals /RAS, /CAS and /WE at a rising of internal clock signal CLK, and generates the operation mode designating signal based on the result of determination. The combination of the states of these control signals is called a "command."
Synchronous semiconductor memory device 100 further includes an address input buffer 110 for taking in an external address signal ADD and generating an internal address signal in synchronization with internal clock signal CLK under the control of control circuit 108; a row selection circuit 112 operating under the control of control circuit 108 to drive an addressed row of memory array 102 to a selected state according to an internal row address signal supplied from address input buffer 110; a column selection circuit 114 operating under the control of control circuit 108 to select a column of memory array 102 according to an internal column address signal from address input buffer 110; a read circuit 116 for reading memory cell data on the column selected by column selection circuit 114 in synchronization with clock signal CLK under the control of control circuit 108; and an output circuit 118 activated under the control of control circuit 108 for sequentially outputting data transferred from read circuit 116.
Column selection circuit 114 changes the received column address signal in a prescribed sequence with the internal column address signal supplied from address input buffer 110 being a leading address, and sequentially selects columns of memory array 102. Read circuit 116 reads and transfers data according to internal clock signal CLK under the control of control circuit 108.
Output circuit 118 is supplied with a high voltage Vpp from an internal high voltage generating circuit 120. This is because, as will be described later in detail, the last output stage of output circuit 118 is composed of n channel MOS transistors, and there is a need to prevent the voltage level reduction of the high level of the output data Q due to a threshold voltage loss of the n channel MOS transistor at the last output stage. Now, an operation of the dock synchronous semiconductor memory device shown in FIG. 22 will be described with reference to a timing chart shown in FIG. 23.
At arising of external clock signal ext.CLK in a clock cycle #1, row address strobe signal /RAS is set at a low (L) level and column address strobe signal /CAS and write enable signal /WE are each set at a high (H) level, and thus an active command is supplied. In response to the supplied active command, command decoder 106 generates and applies to control circuit 108 an array activation instructing signal. According to this array activation instructing signal, control circuit 108 causes address input buffer 110 to take in address signal ADD and to generate an internal row address signal X. Row selection circuit 112 operates under the control of control circuit 108, and drives a word line corresponding to an addressed row of memory array 102 to a selected state according to the internal row address signal X (a word line is provided corresponding to each memory cell row).
When column address strobe signal /CAS is set at an L level and row address strobe signal /RAS and write enable signal /WE are set at an H level at a rising of external clock signal ext.CLK in clock cycle #3, a read command is supplied, which instructs data reading. According to a data reading designation signal from command decoder 106, control circuit 108 causes address input buffer 110 to take in currently applied address signal ADD and to generate an internal column address signal Y.
Column selection circuit 114 sequentially selects columns in memory array 102 in a prescribed sequence with the address signal Y being a leading address. Data of the memory cell selected by column selection circuit 114 is transmitted to read circuit 116. Read circuit 116 sequentially transfers the transmitted data in synchronization with internal clock signal CLK under the control of control circuit 108, and provides the data to output circuit 118. Output circuit 118 is then activated also under the control of control circuit 108, and outputs the data supplied from read circuit 116.
A certain period of time is required for the selection of a memory cell column by column selection circuit 114 as well as transfer of internal read data by read circuit 116. Therefore, read data Q is set at a definite state at a rising of external clock signal ext.CLK in clock cycle #5 after two clock cycles since supplying of the read command. Thereafter, column selection circuit 114 sequentially selects memory cell columns in a prescribed sequence with address signal Y used as a leading address, and data in these memory cells are read out in synchroization with clock signal CLK. Data Q1, Q2 and Q3 become definite at rising of external clock signal ext.CLK in clock cycles #6, #7 and #8, respectively.
Output circuit 118 enters an output high impedance state after a prescribed number of data pieces are read out. The number of data pieces consecutively read out after a read command is supplied is called a burst length; the number of clock cycles required after supplying of the read command until a valid data is output is called a CAS latency.
Reading data out in synchronization with external clock signal ext.CLK enables to transfer data to a processor (not shown) in synchronization with the external clock signal ext.CLK, which permits high-speed data transfer. Accordingly, it becomes possible to prevent degradation of the performance of a processing system due to the difference in operating frequency between a processor and a main memory when a standard DRAM is used as the main memory.
Command decoder 106 may be configured to be supplied with a prescribed bit of address signal ADD. Clock input buffer 104 may be formed of a PLL (Phase Locked Loop), for example. Internal clock signal CLK has only to be a clock signal in synchronization with external clock signal ext.CLK.
FIG. 24 is a diagram schematically showing a configuration of the last stage of output circuit 118 shown in FIG. 22. Referring to FIG. 24, output circuit 118 includes a level conversion circuit 118a for converting the H level of an internal read data RD to a high voltage Vpp level; an n channel MOS transistor 118b connected between a power supply node receiving a power supply voltage Vccq and an output node 118d and having a gate receiving an output signal of level conversion circuit 118a; and an n channel MOS transistor 118c connected between output node 118d and a ground node and having a gate receiving an internal read data ZRD. Internal read data RD and ZRD are data complementary to each other.
Configuration of the last output stage with n channel MOS transistors 118b and 118c avoids the necessity of a region for PN junction isolation, thereby reducing circuit occupation area and implementing a latch-up free circuit. With such a configuration, however, a problem of the threshold voltage loss arises because of n channel MOS transistor 118b used to generate an H level data. Level conversion circuit 118a converts the II level of internal read data RD (internal operation power supply voltage level) into an internal high voltage Vpp level. This internal high voltage Vpp is at a voltage level equal to or higher than Vccq+Vth, in which Vth represents a threshold voltage of n channel MOS transistor 118b. Accordingly, a signal at a level of power supply voltage Vccq can be transmitted to output node 118d, without a threshold voltage loss at MOS transistor 118b.
FIG. 25 is a diagram showing an exemplary configuration of level conversion circuit 118a shown in FIG. 24. With reference to FIG. 25, level conversion circuit 118a includes a p channel MOS transistor PT1 connected between a high voltage supply node and an internal node 118aa and having a gate connected to an internal node 118ab; a p channel MOS transistor PT2 connected between the high voltage supply node and node 118ab and having a gate connected to node 118aa; an n channel MOS transistor NT1 connected between internal node 118aa and a ground node and having a gate receiving internal read data RD; and an n channel MOS transistor NT2 connected between internal node 118ab and the ground node and having a gate receiving internal read data RD via an inverter IV.
Internal read data RD is at an internal power supply voltage level. When internal read data RD is at an H level, an output signal of inverter IV is at an L level, MOS transistor NT1 is in an ON state, and MOS transistor NT2 is in an OFF state. When node 118aa is discharged via MOS transistor NT1, conductance of MOS transistor PT2 increases, and node 118ab is charged via MOS transistor PT2, and has the voltage level thus increased. According to the voltage increase of the node 118ab, conductance of MOS transistor PT1 decreases, and node 118aa is discharged to a ground voltage level at high speed. Consequently, node 118ab ultimately attains the internal high voltage Vpp level, and internal node 118aa attains the ground voltage level. Conversely, if internal read data RD is at the ground voltage level, MOS transistor NT1 is in an OFF state, MOS transistor NT2 is in an ON state, and thus node 118aa attains internal high voltage Vpp level, and internal node 118ab attains the ground voltage level. This node 118ab is connected to a gate of outputting n channel MOS transistor 118b shown in FIG. 24.
Level conversion circuit 118a has only to drive the gate of outputting MOS transistor 118b, and needs only a small current drivability. In a latch state in which one of internal nodes 118aa and 118ab is at internal high voltage Vpp level and the other is at the ground voltage level, a current flowing path is blocked, whereby low current dissipation is realized.
Now, output circuit 118 shown in FIG. 22 is considered to have a configuration that outputs a plurality of bits of output data Q0 to Qn, as shown in FIG. 26. Output buffers 128-0 to 128-n are provided corresponding to output data bits Q0 to Qn, respectively. These output buffers 128-0 to 128-n each have a configuration substantially the same as that shown in FIG. 24. Output buffers 128-0 to 128-n are supplied with outputting power supply voltage Vccq via an external pin terminal 129. Internal high voltage Vpp from internal high voltage generating circuit 120 is commonly applied to the level conversion circuits included in the output buffers 128-0 to 128-n. Due to such application of outputting power supply voltage Vccq from an outside via pin terminal 129, even if output buffers 128-0 to 128-n to operate in parallel to consume a large amount of current, the fluctuation of the power supply voltage will have no effects on other internal circuits, thereby preventing malfunction of the internal circuits. The application of outputting power supply voltage Vccq from the outside also allows a power source for the last stage of output buffers 128-0 to 128n to have a large current drivability, which ensures stable data output even when the data is output in synchronization with high-speed clock signal ext.CLK.
Internal high voltage Vpp is commonly applied to output buffers 128-0 to 128-n from internal high voltage generating circuit 120 provided within the synchronous semiconductor memory device. Level conversion circuit 118a shown in FIG. 24 has only to charge and discharge gate capacitance of outputting MOS transistor 118b, and needs only a small current drivability. However, if the number of output data bits Q0-Qn increases to 16 bits or to 32 bits, for example, current dissipation at the level conversion circuits included in output buffers 128-0 to 128-n at data reading becomes inneligible.
FIG. 27 is a diagram schematically showing a configuration of internal high voltage generating circuit 120 shown in FIGS. 22 and 26. In FIG. 27, internal high voltage generating circuit 120 includes a ring oscillator 120a oscillating at a prescribed cycle, and a charge pumping circuit 120b generating internal high voltage Vpp by a charge pumping operation of a capacitor according to an output signal of ring oscillator 120a. To increase charge supplying capability of internal high voltage generating circuit 120, it is required to increase an oscillating frequency f of ring oscillator 120a and a capacitance value C of a charge pumping capacitor included in charge pumping circuit 120b. The higher the oscillating frequency of ring oscillator 120a is set, the larger a current consumed by switching operation at ring oscillator 120a becomes. In addition, the increase in the capacitance value of the capacitor included in charge pumping circuit 120b leads to increase in capacitor occupation area, and hence in circuit occupation area.
Since design resources for normal standard DRAMs (Dynamic Random Access Memories) are inherited in configuring internal high voltage generating circuit 120, circuit configuration and layout with an osciliating frequency of ring oscillator 120a and a capacitance value of the charge pumping capacitor of charge pumping circuit 120b both optimized for a standard DRAM are employed. Therefore, when a large number of output buffers 128-0 to 128-n are operated in parallel in synchronization with high-speed clock signal ext.CLK, the charge supplying capability is insufficient, and the voltage level of internal high voltage Vpp decreases, making it impossible to drive outputting MOS transistor 118b shown in FIG. 24 to a strong ON state. In this case, even if the threshold voltage loss does not occur, conductance of outputting MOS transistor 118b is not large enough to drive outputting data bits Q0 to Qn to an H level of power supply voltage Vccq level at high speed, thus hindering high speed data reading.
Further, even at the time when internal power voltage Vpp is stably supplied, since the length of an internal interconnection line transmitting the internal high voltage Vpp becomes longer as the number of output buffers 128-0 to 128-n is larger, a large current flows on the internal high voltage transmission line while output buffers 128-0 to 128-n are in operation, and the line resistance of this internal high voltage Vpp transmission line causes the voltage level of internal high voltage Vpp supplied to output buffers 128-0 to 128-n to change. At this time, the output voltage levels of level conversion circuits 118a included in output buffers 128-0 to 128-n change accordingly. As a result, the driving rate of data output bits Q0 to Qn of output buffers 128-0 to 128-n to an H level will vary from each other, thus making impossible to read data at high speed (the data reading speed is determined according to the worst case).